Partial Scan Test Generation for Asynchronous Circuits Based On Breaking Global Loops

Asynchronous circuits without global clocks are hard to test. Scan design methods provide an effective way to test these circuits. Full scan design seems to be a perfect alternative but at the cost of area overhead. So partial scan based design helps to overcome this area overhead problem and giving a better fault coverage. This paper presents a partial scan based ATPG methodology to generate tests for asynchronous circuits with state holding elements other than latches. The partial scan elements selection is adopted from the conventional Cheng’s method based on strongly connected components. One more step of cyclic to acyclic conversion is carried out to generate test patterns for the asynchronous circuits compared to the conventional synchronous circuit test generation. These test patterns are then used to test the original circuit. This method is compared with full scan and other methods with respect to fault coverage and area overhead.